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    pygments.lexers.hdl
    ~~~~~~~~~~~~~~~~~~~

    Lexers for hardware descriptor languages.

    :copyright: Copyright 2006-present by the Pygments team, see AUTHORS.
    :license: BSD, see LICENSE for details.
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fdefdeejeƒfdejfdejfdefdedfdejfdejfdejfdejfdejfdejfdejfdefdejfdefdefdejfdeeeje ƒfdeeeje ƒd fe!d!d"d#�efe!d$d%d"d&�ejfe!d'd(d"d&�ej"fe!d)d"d#�ej#fd*ej$fd+efd,efgd-ed.fd/ejfd0efdeejeƒfd1efgd2ejfd3ejfd4ejd.fd5ejfd6ejfd7ed.fgd8ejd.fgd9œZ%d:d;„ Z&d<S )=r   z?
    For verilog source code with preprocessor directives.
    ÚverilogÚvz*.vztext/x-verilogz%https://en.wikipedia.org/wiki/Verilogz1.4ú(?:\s|//.*?\n|/[*].*?[*]/)+z^\s*`defineÚmacroú\s+ú(\\)(\n)ú/(\\\n)?/(\n|[\s\S]*?[^\\]\n)ú/(\\\n)?[*][\s\S]*?[*](\\\n)?/ú[{}#@]úL?"Ústringú4L?'(\\.|\\[0-7]{1,3}|\\x[a-fA-F0-9]{1,2}|[^\\\'\n])'ú%(\d+\.\d*|\.\d+|\d+)[eE][+-]?\d+[lL]?ú(\d+\.\d*|\.\d+|\d+[fF])[fF]?z([0-9]+)|(\'h)[0-9a-fA-F]+z([0-9]+)|(\'b)[01]+z([0-9]+)|(\'d)[0-9]+z([0-9]+)|(\'o)[0-7]+z\'[01xz]z\d+[Ll]?ú[~!%^&*+=|?:<>/-]ú[()\[\],.;\']ú`[a-zA-Z_]\w*ú^(\s*)(package)(\s+)ú^(\s*)(import)(\s+)Úimport)qÚalwaysÚalways_combÚ	always_ffÚalways_latchÚandÚassignÚ	automaticÚbeginÚbreakÚbufÚbufif0Úbufif1ÚcaseÚcasexÚcasezÚcmosÚconstÚcontinueÚdeassignÚdefaultÚdefparamÚdisableÚdoÚedgeÚelseÚendÚendcaseÚendfunctionÚendgenerateÚ	endmoduleÚ
endpackageÚendprimitiveÚ
endspecifyÚendtableÚendtaskÚenumÚeventÚfinalÚforÚforceÚforeverÚforkÚfunctionÚgenerateÚgenvarÚhighz0Úhighz1ÚifÚinitialÚinoutÚinputÚintegerÚjoinÚlargeÚ
localparamÚmacromoduleÚmediumÚmoduleÚnandÚnegedgeÚnmosÚnorÚnotÚnotif0Únotif1ÚorÚoutputÚpackedÚ	parameterÚpmosÚposedgeÚ	primitiveÚpull0Úpull1ÚpulldownÚpullupÚrcmosÚrefÚreleaseÚrepeatÚreturnÚrnmosÚrpmosÚrtranÚrtranif0Úrtranif1ÚscalaredÚsignedÚsmallÚspecifyÚ	specparamZstrengthr   Ústrong0Ústrong1ÚstructÚtableÚtaskÚtranÚtranif0Útranif1ÚtypeÚtypedefÚunsignedÚvarÚvectoredÚvoidÚwaitÚweak0Úweak1ÚwhileÚxnorÚxorú\b©Úsuffix)Z
accelerateZautoexpand_vectornetsZ
celldefineZdefault_nettyper@   ÚelsifZendcelldefineÚendifZ
endprotectZendprotectedZexpand_vectornetsZifdefZifndefr   ZnoaccelerateZnoexpand_vectornetsZnoremove_gatenamesZnoremove_netnamesZnounconnected_driveZprotectÚ	protectedZremove_gatenamesZremove_netnamesZresetallZ	timescaleZunconnected_driveZundefú`)Úprefixr™   )4ÚbitsZ
bitstorealZbitstoshortrealZcountdriversÚdisplayZfcloseZfdisplayÚfinishÚfloorZfmonitorZfopenZfstrobeZfwriteZ
getpatternÚhistoryZincsaverZ   ZitorÚkeyÚlistÚlogZmonitorZ
monitoroffZ	monitoronZnokeyZnologZprinttimescaleÚrandomZreadmembZreadmemhÚrealtimeZ
realtobitsÚresetZreset_countZreset_valueZrestartZrtoiÚsaveÚscaleÚscopeZshortrealtobitsZ
showscopesZshowvariablesZshowvarsZ	sreadmembZ	sreadmemhZstimeÚstopZstrobeÚtimeZ
timeformatÚwritez\$)ÚbyteÚshortintÚintÚlongintr[   r®   ÚbitÚlogicÚregÚsupply0Úsupply1ÚtriÚtriandÚtriorÚtri0Útri1ÚtriregÚuwireÚwireÚwandÚworÚ	shortrealÚrealr¨   ú[a-zA-Z_]\w*:(?!:)ú\$?[a-zA-Z_]\w*ú\\(\S+)ú"ú#popú/\\([\\abfnrtv"\']|x[a-fA-F0-9]{2,4}|[0-7]{1,3})ú	[^\\"\n]+ú\\ú[^/\n]+ú/[*][\s\S]*?[*]/z//.*?\nú/ú	(?<=\\)\nú\nú	[\w:]+\*?©Úrootr   r   r'   c                 C   s8   d}d| v r|d7 }d| v r$|d7 }d| v r4|d7 }|S )z`Verilog code will use one of reg/wire/assign for sure, and that
        is not common elsewhere.r   r¶   gš™™™™™¹?rÀ   r-   © )ÚtextÚresultrÕ   rÕ   ú9E:\soccer\ml_env\Lib\site-packages\pygments/lexers/hdl.pyÚanalyse_text„   s    zVerilogLexer.analyse_textN)'Ú__name__Ú
__module__Ú__qualname__Ú__doc__ÚnameÚaliasesÚ	filenamesÚ	mimetypesÚurlÚversion_addedÚ_wsr	   ÚPreprocr   r   r   ÚEscapeÚSingleÚ	Multiliner   ÚCharr   ÚFloatÚHexÚBinÚIntegerÚOctr
   r   ÚConstantr   Ú	Namespacer   r   ÚBuiltinÚTypeÚLabelÚtokensrÙ   rÕ   rÕ   rÕ   rØ   r      s�   
ÿïîùø
	÷
öüûµNû
ú	
ÿ£br   c                !   @   s  e Zd ZdZdZddgZddgZdgZdZdZ	d	Z
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eeejƒdfdeeejeƒfdeeejeƒdfdefdeejeƒfdejfdejfdefdedfdejfdejfdejfdejfdejfdejfdejfdefdejfdefed d!d"�ejfd#efd$e j!fed%d!d"�efd&eej"ee j#ƒfd'eej"ee j#ƒfd(eej"eeee j#ƒfed)d!d"�ej$fed*d!d"�ejfed+d!d"�e j%fd,e j&fd-e fd.e fg d/ed0fd1ejfd2efdeejeƒfd3efgd4ejfd5ejfd6ejd0fd7ejfd8ejfd9ed0fgd:e jd0fgd;œZ'd<S )=r   zi
    Extends verilog lexer to recognise all SystemVerilog keywords from IEEE
    1800-2009 standard.
    ÚsystemverilogÚsvz*.svz*.svhztext/x-systemverilogz+https://en.wikipedia.org/wiki/SystemVerilogú1.5r   z^(\s*)(`define)r   r%   r&   r'   r   r   r   r   r   r   r   r   r    r!   z4([1-9][_0-9]*)?\s*\'[sS]?[bB]\s*[xXzZ?01][_xXzZ?01]*z6([1-9][_0-9]*)?\s*\'[sS]?[oO]\s*[xXzZ?0-7][_xXzZ?0-7]*z6([1-9][_0-9]*)?\s*\'[sS]?[dD]\s*[xXzZ?0-9][_xXzZ?0-9]*zB([1-9][_0-9]*)?\s*\'[sS]?[hH]\s*[xXzZ?0-9a-fA-F][_xXzZ?0-9a-fA-F]*z
\'[01xXzZ]z[0-9][_0-9]*r"   )ZinsideÚdistr—   r˜   z[()\[\],.;\'$]r$   )ÒZ	accept_onÚaliasr(   r)   r*   r+   r,   Úassertr-   Zassumer.   Úbeforer/   ÚbindZbinsZbinsofr0   r1   r2   r3   r4   r5   r6   ÚcellÚcheckerZclockingr7   ÚconfigÚ
constraintÚcontextr9   ZcoverZ
covergroupZ
coverpointÚcrossr:   r;   r<   Zdesignr=   r>   r?   r@   rA   rB   Z
endcheckerZendclockingZ	endconfigrC   rD   ZendgroupZendinterfacerE   rF   rG   Z
endprogramZendpropertyZendsequencerH   rI   rJ   rK   Z
eventuallyÚexpectZexportZexternrM   Zfirst_matchrN   rO   ZforeachrP   rQ   ZforkjoinrR   rS   rT   ÚglobalrU   rV   rW   ZiffZifnoneZignore_binsZillegal_binsZimpliesZ
implementsr'   Úincdirr   rX   rY   rZ   ÚinstanceZinterconnectZ	interfaceZ	intersectr\   Zjoin_anyZ	join_noner]   ZletZliblistÚlibraryÚlocalr^   r_   Úmatchesr`   Zmodportra   rb   rc   ZnettypeÚnewZnexttimerd   re   Znoshowcancelledrf   rg   rh   Únullri   rj   Úpackagerk   rl   rm   rn   ro   ÚpriorityÚprogramÚpropertyrœ   rp   rq   rr   rs   Zpulsestyle_ondetectZpulsestyle_oneventÚpureZrandZrandcZrandcaseZrandsequencert   ru   Z	reject_onrv   rw   Zrestrictrx   ry   rz   r{   r|   r}   Zs_alwaysZs_eventuallyZ
s_nexttimeZs_untilZs_until_withr~   ÚsequenceZshowcancelledr€   ZsoftZsolver�   r‚   ZstaticÚstrongrƒ   r„   r…   ÚsuperZsync_accept_onZsync_reject_onr†   Ztaggedr‡   r   Z
throughoutZtimeprecisionZtimeunitrˆ   r‰   rŠ   rŒ   ÚunionÚuniqueZunique0ÚuntilZ
until_withZuntypedÚuser�   Zvirtualr‘   Z
wait_orderZweakr’   r“   r”   ZwildcardÚwithZwithinr•   r–   z(class)(\s+)([a-zA-Z_]\w*)z(extends)(\s+)([a-zA-Z_]\w*)z,(endclass\b)(?:(\s*)(:)(\s*)([a-zA-Z_]\w*))?)!r´   r°   Úchandler8   rL   r²   r[   rµ   r³   rÄ   r¨   r¶   r±   rÃ   r   r   r®   r‹   r�   rŽ   r�   r·   r¸   r¹   rº   r»   r¾   r¼   r½   r¿   rÁ   rÀ   rÂ   )z	`__FILE__z	`__LINE__z`begin_keywordsz`celldefinez`default_nettypez`definez`elsez`elsifz`end_keywordsz`endcelldefinez`endifz`ifdefz`ifndefz`includez`linez`nounconnected_drivez`pragmaz	`resetallz
`timescalez`unconnected_drivez`undefz`undefineall)Äz$exitz$finishz$stopz	$realtimez$stimez$timez$printtimescalez$timeformatz$bitstorealz$bitstoshortrealz$castz$itorz$realtobitsz$rtoiz$shortrealtobitsz$signedz	$unsignedz$bitsz$isunboundedz	$typenamez$dimensionsz$highz
$incrementz$leftz$lowz$rightz$sizez$unpacked_dimensionsz$acosz$acoshz$asinz$asinhz$atanz$atan2z$atanhz$ceilz$clog2z$cosz$coshz$expz$floorz$hypotz$lnz$log10z$powz$sinz$sinhz$sqrtz$tanz$tanhz
$countbitsz
$countonesz
$isunknownz$onehotz$onehot0z$infoz$errorz$fatalz$warningz$assertcontrolz$assertfailoffz$assertfailonz$assertkillz$assertnonvacuousonz
$assertoffz	$assertonz$assertpassoffz$assertpassonz$assertvacuousoffz$changedz$changed_gclkz$changing_gclkz$falling_gclkz$fellz
$fell_gclkz$future_gclkz$pastz
$past_gclkz$rising_gclkz$rosez
$rose_gclkz$sampledz$stablez$stable_gclkz$steady_gclkz$coverage_controlz$coverage_getz$coverage_get_maxz$coverage_mergez$coverage_savez$get_coveragez$load_coverage_dbz$set_coverage_db_namez$dist_chi_squarez$dist_erlangz$dist_exponentialz$dist_normalz$dist_poissonz$dist_tz$dist_uniformz$randomz$q_addz$q_examz$q_fullz$q_initializez	$q_removez$async$and$arrayz$async$and$planez$async$nand$arrayz$async$nand$planez$async$nor$arrayz$async$nor$planez$async$or$arrayz$async$or$planez$sync$and$arrayz$sync$and$planez$sync$nand$arrayz$sync$nand$planez$sync$nor$arrayz$sync$nor$planez$sync$or$arrayz$sync$or$planez$systemz$displayz	$displaybz	$displayhz	$displayoz$monitorz	$monitorbz	$monitorhz	$monitoroz$monitoroffz
$monitoronz$strobez$strobebz$strobehz$strobeoz$writez$writebz$writehz$writeoz$fclosez	$fdisplayz
$fdisplaybz
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$fdisplayoz$feofz$ferrorz$fflushz$fgetcz$fgetsz	$fmonitorz
$fmonitorbz
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$writemembz
$writememhz$test$plusargsz$value$plusargsz$dumpallz	$dumpfilez
$dumpflushz
$dumplimitz$dumpoffz$dumponz
$dumpportsz$dumpportsallz$dumpportsflushz$dumpportslimitz$dumpportsoffz$dumpportsonz	$dumpvarsrÅ   rÆ   rÇ   rÈ   rÉ   rÊ   rË   rÌ   rÍ   rÎ   z//.*?$rÏ   rÐ   rÑ   rÒ   rÓ   N)(rÚ   rÛ   rÜ   rÝ   rÞ   rß   rà   rá   râ   rã   rä   r   r   r	   rå   r   rð   r   ræ   rç   rè   r   ré   r   rê   rì   rî   rí   rë   r
   r   ÚWordr   rï   ÚDeclarationÚClassrò   rñ   ró   rô   rÕ   rÕ   rÕ   rØ   r   ’   s´   ÿÿÿÿ)×*Ö,ÿÿÿ	÷
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ú	
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jB Zdefd	eejeƒfd
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    For VHDL source code.
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'[a-z_]\w*r#   z"[^\n\\"]*"z(library)(\s+)([a-z_]\w*)z(use)(\s+)(entity)z(use)(\s+)([a-z_][\w.]*\.)(all)z(use)(\s+)([a-z_][\w.]*)z(std|ieee)(\.[a-z_]\w*))ZstdZieeeZworkr—   r˜   z"(entity|component)(\s+)([a-z_]\w*)zN(architecture|configuration)(\s+)([a-z_]\w*)(\s+)(of)(\s+)([a-z_]\w*)(\s+)(is)z ([a-z_]\w*)(:)(\s+)(process|for)z
(end)(\s+)ÚendblockÚtypesÚkeywordsÚnumbersz	[a-z_]\w*ú;rÉ   )Úbooleanr´   Ú	characterZseverity_levelr[   r®   Zdelay_lengthZnaturalZpositiver   Z
bit_vectorZfile_open_kindZfile_open_statusZ
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